Kazarlis, Spyros; Kalomiros, John; Mastorocostas, Paris; Petridis, Vassilios; Balouktsis, Anastasios; Kalaitzis, Vassilios; Valais, Antonios
(2014-12)
This work presents a method for simulating
asynchronous digital circuits, of both combinational and
sequential logic, at the gate level. The simulator is going to serve
as a fitness function of an Evolutionary Algorithm ...