Περίληψη:
This work presents a method for simulating
asynchronous digital circuits, of both combinational and
sequential logic, at the gate level. The simulator is going to serve
as a fitness function of an Evolutionary Algorithm that will be
used for optimal synthesis of digital circuits. Therefore the
simulator needs to be simple, fast and reliable. The circuit under
evaluation will be given to the simulator in an encoded form
resembling DNA. Both the circuit codification method and the
simulator are analytically discussed. Results are presented for a
number of combinatorial and sequential digital circuits that prove
the efficiency of the simulation method.