dc.contributor.author | Efstathiou, D. | |
dc.date.accessioned | 2015-06-30T11:40:13Z | |
dc.date.available | 2015-06-30T11:40:13Z | |
dc.date.issued | 2011-07 | |
dc.identifier.other | http://ieeexplore.ieee.org/Xplore/defdeny.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fstamp%2Fstamp.jsp%3Ftp%3D%26arnumber%3D6004945%26isnumber%3D6004864&denyReason=-131&arnumber=6004945&productsMatched=null&userType=inst | el |
dc.identifier.uri | http://apothesis.teicm.gr/xmlui/handle/123456789/1566 | |
dc.description.abstract | Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs. There are several key points required for high performance D-PLL circuits design such as power efficiency, loop bandwidth flexibility and accurate frequency translation. This paper describes a novel D-PLL architecture and presents an analysis of the digital loop filter. | en |
dc.format.extent | 6 | el |
dc.language.iso | en | el |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Διεθνές | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | A digital loop filter for a Phase Locked Loop | en |
dc.type | Άρθρο σε επιστημονικό συνέδριο | el |
dc.conference.information | Corfu, 6-8 July, 2011 | el |
dc.conference.name | Digital Signal Processing (DSP), 17th International Conference on | el |
dc.identifier.doi | 10.1109/ICDSP.2011.6004945 | |
dc.publication.category | Απαγόρευση δημοσίευσης - Βιβλιογραφική αναφορά | el |
dc.subject.keyword | Audio systems | el |
dc.subject.keyword | Broadband networks | el |
dc.subject.keyword | Digital communication | el |
dc.subject.keyword | Digital filters | el |
dc.subject.keyword | Digital phase locked loops | el |
dc.subject.keyword | Network synthesis | el |
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